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W25Q64DW
and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status
Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
During volatile Status Register write operation (50h combined with 01h), after /CS is driven high, the
Status Register bits will be refreshed to the new values within the time period of t SHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
The Write Status Register instruction can be used in both SPI mode and QPI mode. However, the QE bit
cannot be written to when the device is in the QPI mode, because QE=1 is required for the device to enter
and operate in the QPI mode.
Please refer to 10.1 for detailed Status Register Bit descriptions. Factory default for all status Register bits
are 0.
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Mode 3
CLK
Mode 0
Mode 0
Instruction (01h)
Status Register 1 in
Status Register 2 in
DI
(IO 0 )
DO
7
*
6
5 4 3
High Impedance
2
1
0
15
*
14
13
12
11
10
9
8
(IO 1 )
* = MSB
Figure 9a. Write Status Register Instruction (SPI Mode)
/CS
Mode 3
0
1
2
3
4
5
Mode 3
CLK
Mode 0
Mode 0
In structio n
01h
SR1 in
SR2 in
IO 0
IO 1
IO 2
IO 3
4
5
6
7
0
1
2
3
12
13
14
15
8
9
10
11
Figure 9b. Write Status Register Instruction (QPI Mode)
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